1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
Representative test apparatuses for testing a device under test such as a DRAM include a semiconductor test apparatus. For example, Patent Document No. 1 discloses a semiconductor memory test apparatus used for memory repair in a semiconductor memory IC. The semiconductor memory test apparatus described in Patent Document No. 1 stores a test result in the address fail memory while the test continues. After ending of the test, the semiconductor memory test apparatus transfers the test result to the fail buffer memory, to execute the pass/fail analysis. After ending of the transfer of the test result, the next test is started (see Patent Document No. 1). Patent Document No. 2 and Patent Document No. 3 disclose similar technologies.
Patent Document No. 1: Japanese Patent Application Publication No. H11-213695
Patent Document No. 2: Japanese Patent Application Publication No. 2005-267673
Patent Document No. 3: Japanese Patent Application Publication No. 2004-348892
However as the capacity of semiconductor devices increases, transfer of the fail data takes longer, affecting the test throughput. In view of the large ratio of the test cost in the production cost of device under tests, further improvement in test throughput is desirable.